• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a stochastic microprocessor. The microprocessor comprises a stochastic calculation elementary module (1) able to receive two random and independent binary input signals (A, B) each representing a binary coding respectively of two given input probability values, and capable of generating outputting a random binary output signal (C). The basic module comprises: - a programmable logic unit (2) able to combine two input signals (A, B) to generate an output signal (C); an addressable memory (3) capable of storing a coded output probability value by an output signal (C) generated by the logic unit (2); a first clock (4) stochastic, able to produce a first clock signal (CLK1); - A second clock (5) stochastic capable of producing a second clock signal (CLK2).
    公开号:FR3038084A1
    申请号:FR1556102
    申请日:2015-06-29
    公开日:2016-12-30
    发明作者:Jacques Droulez；Pierre Bessiere
    申请人:Centre National de la Recherche Scientifique CNRS；College de France；
    IPC主号:
    专利说明:

    [0001] The present invention relates to a stochastic microprocessor, in particular for performing parallel computations. In particular, it finds application to areas in which probability calculation and uncertainty management are important factors, such as financial markets, macroeconomic modeling, weather forecasting, modeling of macroeconomic modeling. long-term evolution. It is also applicable to the fields in which learning methods are used, for example in the case of genetic algorithms, in particular in robotics and artificial intelligence. It still finds an application in the field of cryptography. In general, the invention finds application to any field in which intensive computations of a probabilistic or stochastic nature are required. Today, conventional microprocessors used in known computer systems have reached a higher physical limit in terms of computational speed. Indeed, the speed of light imposes a higher limit on the clock rate. Since 2000, the clock rate of conventional microprocessors stagnates at 3 or 4 GHz. Moreover, these conventional microprocessors have also reached a lower physical limit in terms of miniaturization. Indeed, the etch dimensions of the integrated circuits do not fall below the 10 nm threshold below which the behavior of the logic circuits becomes unstable and non-deterministic. Also, the logic circuits can not be miniaturized further without questioning their reliability.
    [0002] To overcome these limits and meet ever increasing needs in computing power, it is possible to operate in parallel a large number of processors. But the systems based on this operation are expensive, bulky, impose a suitable infrastructure and consume a large amount of energy. In addition, concerning more particularly energy consumption, the notion of thermal noise plays an important role. Indeed, below the "bar" of the thermal noise, it is no longer possible to assign a deterministic behavior to the transistors of which are constituted most of the components of a conventional microprocessor. In addition, today, a growing number of applications rely heavily on probability calculations and uncertainty management. These applications are very expensive in computing power, when they are implemented on conventional computer systems because the latter are designed to operate in a completely deterministic manner. However, whatever the field of application, the simulation by large-scale probabilistic models is currently carried out by deterministic machines comprising a very large number of interconnected processors, according to cluster or supercomputer architectures, in very large installations. costly and term infrastructure and energy consumption, with significant needs especially in terms of air conditioning and cooling of "multicore". One of the aims of the invention is therefore to solve the aforementioned problems. Thus, one particular object of the invention is to propose a microprocessor making it possible to remove the technological locks presented above, by abandoning the perfectly deterministic operating constraint. The object of the invention is therefore, according to a first aspect, a microprocessor comprising at least one elementary stochastic calculation module capable of receiving at least two random and independent binary input signals, each representing a binary coding of two values respectively. of the input data probability, and able to output at least one random bit output signal from two input signals The elementary module comprises at least one programmable logic unit, able to combine two input signals to generate an output signal according to at least one determined logical function, such that the output signal represents a binary coding of an output probability value as a function of the given input probability values. The elementary module also comprises at least one addressable memory 25 capable of storing a coded output probability value by an output signal generated by the logic unit. The elementary module further comprises at least a first stochastic clock, capable of producing a first random pulse clock signal for controlling the write speed, in the memory, of an output probability value coded by the output signal. generated by the logical unit. The elementary module also comprises at least a second stochastic clock capable of producing a second random pulse clock signal for controlling the reading speed of the memory, so as to provide the current evaluation, over a given time window, of a output probability value stored in the memory.
    [0003] According to some embodiments, the microprocessor furthermore comprises one or more of the following characteristics, taken separately or in any technically possible combination: the elementary module is able, on the one hand, to receive signals as input Random and independent bit input signals each representing stochastic pulse-code or telegraphic time-binary coding respectively of the two given input probability values, and on the other hand outputting a random telegraph-like bit output signal or pulse, and the logic unit is adapted to combine the two input signals to generate the output signal according to the determined logic function, so that the output signal represents stochastic pulse binary coding or telegraphic time binary coding. the probability value at the output according to the probab values data input; the logic unit is able to combine the two input signals to generate the output signal according to one or more of the product, sum and division functions, so that the output probability value encoded by the signal of output corresponds respectively to the product, to the sum and to the division, of the probabilities values in inputs coded respectively by the two input signals; the microprocessor comprises several elementary modules as presented above, and it is capable of generating in parallel at least two output signals by means of at least two elementary modules determined from among said elementary modules, so as to enable parallel implementation of at least two corresponding stochastic calculations; the at least two determined elementary modules are interconnected so as to allow the exchange of signals between them; The memory of at least one of the two interconnected elementary modules is able to store interconnection instructions relating to the interconnection and the exchange of input and output signals between the two interconnected elementary modules; the microprocessor comprises at least two remote elementary modules, and one or more addressable switch boxes in order to allow the exchange of input and output signals between the two remote elementary modules; the microprocessor comprises one or more random signal generators each capable of generating a random binary signal representing a binary coding of a probability value associated with a binary number, and the elementary module or modules are able to receive as input two signals of random and independent binary inputs 35 generated by the random signal generator (s).
    [0004] According to a second aspect, the subject of the invention is also a computer system comprising at least one central memory capable of storing instructions and at least one central computing unit capable of executing instructions stored in the central memory. central processing unit comprising at least one microprocessor as presented above. Thus, the microprocessor of the invention combines, on the same substrate, conventional components with deterministic behavior, such as logic gates, addressable memories and latches, and nano-components exhibiting random behavior, which makes it possible to increase considerably performance in terms of probabilistic calculations while reducing the costs of manufacturing, maintenance, operation and energy consumption. In the case of an architecture with several elementary modules operating in parallel, the stochastic microprocessor of the invention gathers within the same integrated circuit a large number of clocks and components generating random events, as well as large number of memories and logic circuits. The stochastic nature of the events removes the synchronization lock and makes it possible to carry out a large number of operations in parallel. Indeed, the high degree of parallelism that allows the use of random clocks greatly increases performance.
    [0005] Thus, compared with a conventional architecture microprocessor, the microprocessor of the invention makes it possible to perform probabilistic and stochastic calculations much more quickly. More generally, the abandonment of the perfectly deterministic and predictable operating constraints of conventional microprocessors makes it possible to use the microprocessor of the invention to generate and simulate stochastic processes on a very large scale, thus making it possible to widely extend the domain of FIG. application of Monte Carlo simulations of complex phenomena and to solve or approach probabilistic inference problems involving a large number of random variables, such as those posed by financial markets, macroeconomic models, weather forecasts, or long-term evolution models. The microprocessor of the invention also makes it possible to generate, in a non-algorithmic or partially algorithmic manner, random numbers drawn from any distribution. The characteristics and advantages of the invention will appear on reading the following description, given solely by way of example and without limitation, with reference to the following appended figures: FIG. 1: schematic representation of the architecture of an elementary stochastic calculation module in an exemplary microprocessor according to the invention; FIGS. 2 to 6: schematic representations of examples of elementary logic components forming all or part of a programmable logic unit of a stochastic elementary calculation module in a microprocessor according to the invention. A microprocessor according to the invention comprises at least one elementary module 1 for stochastic calculation as represented in an example in FIG. 1. This elementary module can receive as input two input signals A, B, or more.
    [0006] These input signals A, B are random and independent bit signals each representing a binary coding respectively of two given input probability values. Two types of elementary coding for probability values can be used: stochastic pulse coding and telegraphic time coding.
    [0007] With stochastic pulse coding, the signals have a series of ultra-short pulses so that the probability of observing a pulse at any one time is a function of the coded probability value. Thus, with this type of coding, the number of pulses observed during a given time interval provides an estimate of the value of the coded probability.
    [0008] The longer the determined time interval is, in view of the average frequency of the pulses, the greater the accuracy of the coding of the probability value. With telegraphic time coding, the signals alternate randomly between the two states 0 and 1 so that the accumulated time during which the signal is in state 1 relative to the total duration of the determined observation time interval. is equal to the coded probability value. These two types of coding of the probability values are complementary. They are both based on electrical signals of a binary nature, thus compatible with conventional logic circuits. There are no theoretical constraints on the statistical distribution of the time intervals between two successive pulses in a pulse signal, or between two state transitions in a telegraph signal. In particular, a distribution according to a Poisson statistic is quite suitable. In this case, a clock generating stochastic pulses will be defined by a single parameter: the average frequency. The duration of the pulses may be as short as possible, but must remain sufficient to allow the state transition of the flip-flops.
    [0009] 3038084 6 The physical processes responsible for the random behavior of the components must be independent of each other. In particular, they must not generate temporal correlation between two distinct signals. The microprocessor according to the invention may comprise one or more random signal generators, not shown in FIG. 1, each of which makes it possible to generate a random binary signal representing a binary coding, for example according to one of the types presented above, a probability value associated with a binary number. The elementary module 1 then receives as input the input signals A, B generated by the random signal generator or generators.
    [0010] The elementary module 1 is able to output at least a random binary output signal C, from the two input signals A, B. This elementary module 1 furthermore comprises at least one programmable logic unit 2. This logic unit 2 comprises a certain number of conventional logic components 15 organized according to a specific logical architecture, so as to enable the generation of the output signal C according to at least one logical function determined from the combination of the input signals A. Thus, the output signal C represents a binary coding of an output probability value which is a function of the input probability values encoded respectively by the input signals A, B. According to the function performed by the 2, and depending on the nature of the input signal A and the nature of the input signal B, the output signal C represents a stochastic pulse binary coding or a telegraphic time binary coding of the output probability value according to the values probability of entry.
    [0011] FIGS. 2 to 6 show examples of elementary logic components that can form all or part of the logic unit 2 of the elementary module 1. In general, the microprocessor of the invention must make it possible to perform any kind of probabilistic calculation using the random signals A, B. However, in probability theory, any calculation is based on the combination of three rules, simple to state but which prove to be expensive to implement with a conventional microprocessor. The first rule is the product rule, or Bayes rule, in which the joint probability of two variables A, B is equal to the product of the probability of a first of the two variables A, B by the probability of the other conditioned. by the first: P (A & B) = P (A). P (B 1A) = P (B). P (AB) 3038084 7 The second rule is the rule of the sum, or marginalization rule, that the probability distribution on a first variable A is equal to the sum of the joint probabilities of the first variable A and a second one. variable B for all the possible values of the second variable B. Thus, if the second variable B 5 can take n values from 1 to n, the rule of the sum gives: P (A) = P (A & B = 1) + P (A & B = 2) + + P (A & B = n-1) + P (A & B = n) The third rule is the rule of normalization. It results from the constraint imposed in probability theory that the sum of the probabilities of all the possible values of a variable must be equal to 1. However, it is often easier to perform calculations to a multiplicative factor. This rule of normalization therefore requires dividing the intermediate proportional calculation results by a normalization factor, so that the final sum of the probabilities for all the possible values of the variable concerned is equal to 1. Thus, the microprocessor of the The invention is intended to perform the equivalent of the product, sum, and division operations on the random physical signals representing the probability values. These three operations can be performed by logic circuits, implemented in the logic unit 2, taking as input two stochastic signals, or random, telegraphic or pulse type as seen above.
    [0012] By way of example, illustrated in FIGS. 2 and 3, the product can be produced by an "AND" logic gate taking as input two independent random signals, both of telegraphic type (FIG. 3), or one of telegraphic type and the other impulse type (Figure 2). Thus, in the example of FIG. 2, a logic gate "AND" receives as input a telegraph signal A whose probability of being worth 1 is denoted by P (A = 1), and a pulse signal B whose average frequency is noted FB. The two input signals A and B are random and independent. The output signal C is then a random pulse signal whose average frequency Fc is the product of the average frequency of the input B pulse signal and the probability of being 1 of the telegraph input signal A: Fc = Fg. P (A = 1) In other words, the average frequency Fc of the output signal C is equal to the product of the average frequency FB of the signal at the input B by the time spent by the input signal A in the state 1 referred to total observation time.
    [0013] Moreover, as illustrated by the example in FIG. 2, an "AND" logic gate constitutes a basic logic component making it possible to convert a telegraphic type A or B input signal into a pulse type output signal C. In the example of FIG. 3, an "AND" logic gate receives as input two telegraph signals A and B, whose respective probabilities of being worth 1 are denoted P (A = 1) and P (B = 1). The two input signals A and B are random and independent. The output signal C is then a random telegraph signal whose probability of being 1 is the product of the probability of being worth 1 of the telegraphic signal at the input A and the probability of being worth 1 of the telegraphic signal at the input B: 10 P (C = 1) = P (A = 1). P (B = 1) In other words, the output signal C is such that the time spent in the state 1 relative to the total observation time is equal to the product of the time spent by the input signal A in the state 1 by the time spent by the input signal B each related to the total observation time.
    [0014] It will be recalled that the foregoing is true provided that the condition of temporal independence of the physical processes underlying the generation of the random signals A, B, mentioned above, is respected. By way of example, illustrated in FIG. 4, the sum can be realized by an "OR" logic gate taking as input two random signals A and B independent, that is to say, temporally decorrelated, both of the type pulse. Thus, in this example of FIG. 4, an "OR" logic gate receives as input these two impulse signals A and B whose respective average frequencies are denoted FA and FB. The two input signals A and B are random and independent. The output signal C is then a random pulse signal whose average frequency Fc is the sum of the respective average frequencies of the input pulse signals A and B: Fc = FA + FB By way of example, illustrated in FIG. the division operation can be performed by a toggle gate (1-bit memory) taking as input two random signals A and B temporally decorrelated, both pulse type, one on the input S ("set") and the other on the R input ("reset"). In this example of FIG. 5, the flip-flop receives as input the two impulse signals A and B, whose respective average frequencies are denoted FA and FB. The two input signals A and B are random and independent.
    [0015] The output signal C is then a random telegraph signal whose coast, that is to say the probability that the output signal C is equal to the probability that this output signal C is equal to 0, is equal to at the average frequency of the input signal A relative to the average frequency of the input signal B: P (C = 1) / P (C = 0) = FA / Fg In other words, an output signal C of type telegraphic, such that, on average, the time spent in state 1 relative to the time spent in state 0 is equal to the quotient of the average frequencies FA and FB of the input pulse signals A and B. Moreover, as illustrated by the example in FIG. 5, a flip-flop, or 1-bit memory, constitutes a basic logic component making it possible to convert a pulse-type input A or B signal into a telegraphic output signal C.
    [0016] In the example of FIG. 6, two independent and random input telegraph signals A and B are all firstly combined by passing through a first AND logic gate, as in the example of FIG. At the same time, two telegraph signals at input A and U, respective complementary of the input signals A and B, also random and independent, are combined by passing through a second logic gate "AND", also as in the example of FIG. 3. The random telegraph signals at the output of the first and second logic gates "AND" are each recombined with a random pulse signal in two other logic gates "AND". At the output of these two other logic gates 20 "AND" two random pulse signals are obtained, which are combined by passing through a flip-flop (or 1-bit memory) as in the example of FIG. 5. The output signal C of this flip-flop is then a random telegraph signal whose coast, that is to say the probability that the output signal C is equal to the probability that this output signal C is equal to 0, is equal to the product of the coasts of the signals Telegraphic input A and B: P (C = 1) / P (C = 0) = [P (A = 1) / P (A = 0)]. [P (B = 1) / P (B = 0)] Referring again to FIG. 1, the elementary module 1 furthermore comprises at least one addressable memory 3, which makes it possible to store the coded output probability values. by the output signals C generated by the logical unit 2.
    [0017] A first stochastic clock 4 is used to control the writing in the memory 2. To do this, the first clock 4 produces a first random pulse clock signal CLK1 which is inputted by the memory 3 in parallel with the output signal. C of the logic unit 2. The pulses of the signal CLK1 thus make it possible to control the writing of the output probability value coded by the output signal C.
    [0018] A second stochastic clock 5 is used to control the reading in the memory 3. To do this, the second clock 5 produces a second random pulse CLK2 clock signal which is received by the memory 3. The CLK2 signal pulses Thus, it is possible to provide the current evaluation, over a given time window, of an output probability value stored in the memory 3. For complex probabilistic calculations, a large number of sum, product and division operators are involved. required. In this case, the microprocessor of the invention comprises several elementary modules 1 as described above, interconnected. Each elementary module) thus constitutes an elementary unit of stochastic calculus. In this case, we will speak of a stochastic parallel microprocessor. The latter is capable of generating in parallel several output signals C by means of a plurality of elementary modules 1 determined from the set of elementary modules 1 which it comprises so as to enable the parallel implementation of several stochastic calculations each corresponding to one of the elementary modules 1 determined.
    [0019] The microprocessor of the invention with several interconnected elementary modules 1 therefore comprises one or more stochastic components, one or more flip-flops, several addressable memories 3, and different logic circuits implemented in the different programmable logic units 2. The logic circuits implemented in the logical units 2 define the functions that can be performed by the corresponding elementary modules 1. The interconnection between elementary modules 1 is made so that two elementary modules 1 physically adjacent to the substrate can exchange input and output signals A, B, C. Precisely, the memory 3 of an interconnected elementary module 1 with another elementary module 1 contains interconnection instructions which are related to how the two elementary modules 1 will exchange input and output signals A, B, C and the routing of these signals. one elementary module to another. Furthermore, the memory 3 of any elementary module 1 contains the specification of the function or functions to be applied to the input signals A, B by the logic unit 2 to obtain the output signal C. Furthermore, the microprocessor also includes, apart from the stochastic elementary module (s) 1, one or more address decoding circuits, and a deterministic clock for synchronizing the read and write cycles of the memories 3.
    [0020] For the exchange between remote elementary modules 1, it is possible to provide addressable switch boxes, to allow the exchange of input and output signals A, B, C between these remote elementary modules 1. The interconnections between neighboring or distant elementary modules 1 make it possible to carry two types of signals: random telegraphic signals, such as those produced at the output of a flip-flop, and random pulse signals such as those generated by the stochastic clocks. For initialization and modification of the content of the addressable memories 3, various specific input / output modules can be used. Thus, for programming, the microprocessor of the invention can be interfaced with a conventional computer. In this case, the microprocessor is considered as a device specialized in intensive probabilistic computing. A stochastic parallel microprocessor according to the invention therefore associates, on the same substrate, conventional components with deterministic behavior, such as logic gates, addressable memories and latches, which can be produced according to the usual technology of field effect transistors (FETs). , MOSFETs), and nanocomponents exhibiting random behavior for the generation of random signals, which signals can be combined and manipulated by conventional logic circuits.
    [0021] Different physical processes can be used for the realization of stochastic clocks and components at a nanometric size: tunnel effect, capture or emission of photons, or simply exploitation of the unstable behavior of undernourished or nano-sized transistors. Such a stochastic parallel microprocessor makes it possible to represent and manipulate probability distributions at the most fundamental level: that of electrical signals and nano-components. Stochastic electrical signals are indeed a natural support for probabilistic information. The present description is given by way of example and is not limiting of the invention.
    [0022] In particular, the simple logic circuits represented in FIGS. 2 to 6 are only examples of logic circuits that can be implemented in the programmable logic units 2 of the elementary modules 1 of a microprocessor according to the invention. 35
    权利要求:
    Claims (9)
    [0001]
    CLAIMS 1. A microprocessor comprising at least one stochastic calculation elementary module (1) capable of receiving at least two random and independent binary input signals (A, B) each representing a binary coding respectively of two input probability values. data, and able to output at least one random binary output signal (C) from two input signals (A, B), characterized in that said elementary module (1) comprises: at least one logical unit (2) programmable, able to combine two input signals (A, B) to generate an output signal (C) according to at least one logic function determined, so that the output signal (C) represents a binary coding of an output probability value according to the given input probability values; at least one addressable memory (3) capable of storing a coded output probability value by an output signal (C) generated by the logical unit (2); at least a first stochastic clock (4) capable of producing a first random pulse clock signal (CLK1) for controlling the write speed in the memory (3) of an output probability value coded by the output signal (C) generated by the logic unit (2); at least one second stochastic clock (5) capable of producing a second random pulse clock signal (CLK2) for controlling the reading speed of the memory (3), so as to provide the current evaluation, over a given time window , an output probability value stored in the memory (3).
    [0002]
    2. Microprocessor according to claim 1, characterized in that the elementary module (1) is able, on the one hand to receive at input random input and independent input signals (A, B) each representing a pulse binary coding stochastic or a telegraphic time binary coding respectively of the two given input probability values, and secondly to output a random (C) binary output signal, of telegraphic or pulse type, and in that the logical unit (2) is able to combine the two input signals (A, B) to generate the output signal (C) according to the determined logic function, so that the output signal (C) represents a stochastic pulse binary coding or a telegraphic time binary coding of the output probability value according to the given input probability values. 3038084 13
    [0003]
    3. Microprocessor according to any one of claims 1 and 2, characterized in that the logic unit (2) is able to combine the two input signals (A, B) to generate the output signal (C) according to one or more of the product, sum and division functions, so that the output probability value encoded by the output signal (C) corresponds respectively to the product, to the sum and to the division, of the values of probabilities in inputs coded respectively by the two input signals (A, B).
    [0004]
    4. Microprocessor according to any one of claims 1 to 3, characterized in that it comprises several elementary modules (1) according to any one of claims 1 to 3, and in that it is able to generate in parallel at least two output signals (C) through at least two elementary modules (1) determined from said elementary modules (1), so as to allow the parallel implementation of at least two corresponding stochastic calculations. 15
    [0005]
    5. Microprocessor according to claim 4, characterized in that the at least two elementary modules (1) determined are interconnected so as to allow the exchange of signals between them. 20
    [0006]
    6. Microprocessor according to claim 5, characterized in that the memory (3) of at least one of the two interconnected elementary modules (1) is able to store interconnection instructions relating to interconnection and exchange input and output signals (A, B, C) between the two interconnected elementary modules (1). 25
    [0007]
    7. Microprocessor according to any one of claims 4 to 6, characterized in that it comprises at least two remote elementary modules (1), and in that it comprises one or more addressable switch boxes in kind of allow the exchange of input and output signals (A, B, C) between the two remote elementary modules (1). 30
    [0008]
    8. Microprocessor according to any one of claims 1 to 7, characterized in that it comprises one or more random signal generators each adapted to generate a random binary signal representing a binary coding of a probability value associated with a binary number, and in that the elementary module (s) (1) are capable of receiving as input two random and independent binary input signals (A, B) generated by the random signal generator (s). 3038084 14
    [0009]
    9. Computer system comprising at least one central memory capable of storing instructions and at least one central computing unit capable of executing instructions stored in the central memory, characterized in that the central calculation unit comprises at least one microprocessor according to one of claims 1 to 8.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3314394B1|2019-07-03|Stochastic parallel microprocessor
    Bengio et al.2010|Decision trees do not generalize to new variations
    US10664745B2|2020-05-26|Resistive processing units and neural network training methods
    Drechsler et al.2011|Improving ESOP-based synthesis of reversible logic using evolutionary algorithms
    KR20160132943A|2016-11-21|Solving digital logic constraint problems via adiabatic quantum computation
    US10095661B2|2018-10-09|String processor
    Mansinghka et al.2008|Stochastic digital circuits for probabilistic inference
    FR3038997A1|2017-01-20|DATA PROCESSING DEVICE WITH VALUE REPRESENTATION THROUGH INTERVALS OF TIME BETWEEN EVENTS
    US8792602B2|2014-07-29|Mixed signal stochastic belief propagation
    Yang et al.2017|Design of accurate stochastic number generators with noisy emerging devices for stochastic computing
    FR2792141A1|2000-10-13|METHOD FOR SECURING ONE OR MORE ELECTRONIC ASSEMBLIES IMPLEMENTING A SAME CRYPTOGRAPHIC ALGORITHM WITH SECRET KEY, A USE OF THE PROCEDURE AND THE ELECTRONIC ASSEMBLY
    Cambria et al.2017|Storages are not forever
    Khokhar et al.2018|Nanoscale memristive crossbar circuits for approximate edge detection in smart cameras
    Göncü et al.2018|A high speed true random number generator with cellular automata with random memory
    Deb et al.2015|An efficient reduction of common control lines for reversible circuit optimization
    Hawash et al.2012|Using hasse diagrams to synthesize ternary quantum circuits
    EP2936302A1|2015-10-28|Chaotic sequence generator
    Sangeetha et al.2020|An implementation of KFDD based reversible logic using IBM-Q experience
    Chattopadhyay et al.2014|Ancilla-quantum cost trade-off during reversible logic synthesis using Exclusive Sum-of-Products
    Staney et al.2017|Ptl-and clock-pulse circuit driven novel shift register architecture
    Christiani et al.2016|Towards a scalable neuromorphic hardware for classification and prediction with stochastic no-prop algorithms
    EP3622445B1|2021-06-09|Method, implemented by computer, for searching for rules of association in a database
    Yan et al.2020|A novel quantum color image encryption scheme based on controlled alternate quantum walks
    Tara et al.2017|Nanotechnology-Based Efficient Fault Tolerant Decoder in Reversible Logic
    Kissinger2020|Work in Progress: MLL+ MIX as a logic of influence and causation
    同族专利:
    公开号 | 公开日
    JP6916119B2|2021-08-11|
    EP3314394B1|2019-07-03|
    CN107850998B|2021-08-06|
    FR3038084B1|2017-12-29|
    JP2018525726A|2018-09-06|
    US20180196642A1|2018-07-12|
    KR20180021744A|2018-03-05|
    CN107850998A|2018-03-27|
    WO2017001212A1|2017-01-05|
    US10437561B2|2019-10-08|
    EP3314394A1|2018-05-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    GB1184652A|1966-03-07|1970-03-18|Standard Telephones Cables Ltd|Stochastic Computing Arrangement.|
    IL129655D0|1996-10-31|2000-02-29|Discovision Ass|Digital receiver|
    JP3848573B2|2000-01-18|2006-11-22|インフィネオンテクノロジーズアクチエンゲゼルシャフト|Microprocessor system|
    US6745219B1|2000-06-05|2004-06-01|Boris Zelkin|Arithmetic unit using stochastic data processing|
    CN1323113A|2001-01-19|2001-11-21|深圳市中兴集成电路设计有限责任公司|Pseudo-random noise sequence generator with simple structure|
    JP5018757B2|2008-12-09|2012-09-05|富士通株式会社|Parallel-serial converter and data receiving system|
    WO2011103565A1|2010-02-22|2011-08-25|Lyric Semiconductor, Inc.|Mixed signal stochastic belief propagation|US10520975B2|2016-03-03|2019-12-31|Regents Of The University Of Minnesota|Polysynchronous stochastic circuits|
    US10740686B2|2017-01-13|2020-08-11|Regents Of The University Of Minnesota|Stochastic computation using pulse-width modulated signals|
    US11018689B2|2017-10-19|2021-05-25|Regents Of The University Of Minnesota|Parallel computing using stochastic circuits and deterministic shuffling networks|
    US10763890B2|2017-11-10|2020-09-01|Regents Of University Of Minnesota|Computational devices using thermometer coding and scaling networks on unary encoded data|
    US10996929B2|2018-03-15|2021-05-04|Regents Of The University Of Minnesota|High quality down-sampling for deterministic bit-stream computing|
    法律状态:
    2016-05-24| PLFP| Fee payment|Year of fee payment: 2 |
    2016-12-30| PLSC| Publication of the preliminary search report|Effective date: 20161230 |
    2017-05-23| PLFP| Fee payment|Year of fee payment: 3 |
    2018-06-27| PLFP| Fee payment|Year of fee payment: 4 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1556102A|FR3038084B1|2015-06-29|2015-06-29|STOCHASTIC PARALLEL MICROPROCESSOR|FR1556102A| FR3038084B1|2015-06-29|2015-06-29|STOCHASTIC PARALLEL MICROPROCESSOR|
    US15/740,983| US10437561B2|2015-06-29|2016-06-17|Stochastic parallel microprocessor|
    CN201680038921.4A| CN107850998B|2015-06-29|2016-06-17|Random parallel microprocessor|
    JP2017568453A| JP6916119B2|2015-06-29|2016-06-17|Parallel stochastic microprocessor|
    PCT/EP2016/064023| WO2017001212A1|2015-06-29|2016-06-17|Stochastic parallel microprocessor|
    KR1020177037919A| KR20180021744A|2015-06-29|2016-06-17|Probabilistic parallel microprocessor|
    EP16731110.9A| EP3314394B1|2015-06-29|2016-06-17|Stochastic parallel microprocessor|
    [返回顶部]